Particular embodiments generally relate to analog-to-digital (ADC) architectures and more specifically to two-step subranging ADC architectures.
A two-step subranging ADC architecture performs an analog-to-digital conversion in two steps. FIG. 1 depicts a conventional two-step subranging ADC architecture 100. Architecture 100 includes a coarse ADC 102 and a fine ADC 104. Coarse ADC 102 includes a coarser or poorer resolution than fine ADC 104 and can quickly determine an approximate subrange that a sample of an input analog signal falls within. This narrows the range of analog voltages in which the sample of the input analog signal may correspond. Fine ADC 104 then further defines the analog voltage from within the subrange selected by coarse ADC 102.
The input analog signal is received at a track-and-hold stage (MI) 106. Track-and-hold stage 106 tracks the input analog signal and stores an input voltage for the sample of the input analog signal. For example, the input analog signal may be sampled for a half clock cycle and the input voltage from the sample is stored for another half clock cycle.
Coarse ADC 102 compares the stored voltage to a plurality of coarse references received from a reference ladder 108. Reference ladder 108 may include a plurality of tap points. Each tap point may be at a different voltage level for each coarse reference. Coarse ADC 102 performs a first comparison of the input voltage to the coarse references to determine a subrange in which the input voltage falls within.
A result of the first comparison is then used to select finer references or finer subdivisions of the selected subrange for fine ADC 104. For example, certain switches in a switch matrix 110 are closed to provide a second subrange of fine references to fine ADC 104. Fine ADC 104 then performs a second comparison of the fine references and the input voltage.
Encoding and digital correction logic 112 uses the results of the first comparison and the second comparison to determine a first digital code and a second digital code. The first and second digital codes are used to determine a digital output for the sample of the input analog signal. For example, the first and second digital codes may be appropriately weighted, error corrected, and combined to generate the digital output, which may be a digital representation of the sample of the input analog signal.
The determination of the first digital code and second digital code each needs to be made within a half clock period, T/2, where T is a clock period. When the sampling rate goes up, the time that coarse ADC 102 needs to make a decision becomes a larger part of its half clock period T/2.
Reference ladder 108 needs time to settle from a voltage level of a previous sample to set up the fine references. FIG. 2 shows a timing diagram for the conventional two-step subranging architecture 100. At each clock cycle, the input analog signal is tracked (T) and held (H). During the hold period, coarse ADC 1-102 makes its decision within a portion of the T/2 period. Then, in the remaining part of the same T/2 period, coarse output encoding, fine reference selection and subsequent setting of the fine reference takes place. When the sampling rate goes up, coarse output encoding, fine reference selection and subsequent setting of the fine reference combined together take a longer part of the T/2 period, which means less time for reference settling is allotted.
The reference settling problem is discussed in more detail in FIG. 3, which shows a more detailed conventional architecture for a two-step subranging ADC. Reference ladder 1-108 includes a plurality of reference segments 202a-202n. Each reference segment includes a coarse tap 204 to coarse ADC 1-102. Coarse taps 204a-204n provide the coarse references to coarse ADC 1-102. Also, each reference segment 202 includes a plurality of fine taps 206 to provide fine references. When coarse ADC 1-102 makes a coarse decision, switch matrix 1-110 selects a reference segment 202. The selected fine references associated with the selected reference segment 202 are then input into fine ADC 1-104 through switch matrix 1-110.
When the two-step subranging ADC architecture 1-100 is running at very high sampling rates, the maximum conversion rate is limited by the reference settling speed of reference ladder 1-108. Reference settling becomes a speed bottleneck due to loading from a large number of switches in switch matrix 1-110 and comparators in coarse ADC 1-102 or fine ADC 1-104. These loadings dynamically disturb the voltage levels of reference ladder 1-108 decreasing the bandwidth of reference ladder 1-108 and causing a longer settling time. The speed bottleneck becomes a problem as both ADC resolution and conversion rate become higher. To lower the reference settling time, each reference segment 202 may be designed with a very small resistance value. However, designing reference segments with the small resistance value takes up a very large chip area. Also, the resistors of reference segments 202 have their own parasitic capacitance, which limits the return on the lower resistance values.